Counting Modes¶
The fast counter can be configured as one mode out of 10 possible modes. The desired operating mode is selected in the PLC configuration using configuration parameters. Inputs and outputs which are not used by the counters are available for other tasks. In the following table, A means input channel A, B means input channel B and C means output channel C.
| CPUs | Integrated fast counter | Assigned inputs | Assigned Outputs | Remarks | |
|---|---|---|---|---|---|
| Channel A | Channel B | Channel C | |||
| PM55x, PM56x | Yes | Input channel 0 | Input channel 1 | Output channel 0 | Only 1 fast counter is available on the module. Input channel 0 is the default channel for fast counter. Input channel 1 can be used as another fast counter channel depending on fast counter mode. |
| Operating Mode | Function | Input channels | Description | Counting frequency (max.) for PM5x4-T and PM5x4-R |
|---|---|---|---|---|
| 0 | No counter | None | Fast counter is disabled | - |
| 1 | 1 Up counter | A = Counter input C = End value reached |
Counting up A from 0 to 0xFFFFFFFF When the end value is reached, C will be set to high. | 30 kHz (before firmware V2.0.6) 50 kHz (since firmware V2.0.6) |
| 2 | 1 Up counter with release input | A = Counter input B = Enable input C = End value reached |
Counting up A from 0 to 0xFFFFFFFF The counter is enabled if B is high When the end value is reached, C will be set to high. | 30 kHz (before firmware V2.0.6) 50 kHz (since firmware V2.0.6) |
| 3 | 2 Up/Down counters | A = Counter input 1 B = Counter input 2 |
2 independent counters. Status “End value reached” is only readable from the 2 status bytes, not from output terminals. The counting direction is defined by the boolean parameters UD1 and UD2 of Function Block ONB_IO_CNT (Handle Fast Counter on Onboard I/O) | 30 kHz (before firmware V2.0.6) 50 kHz (since firmware V2.0.6) |
| 4 | 2 Up/Down counters (2nd on falling edges) | A = Counter input 1 B = Counter input 2 |
Same as operating mode 3, but counting input B is inverted (counts at TRUE/FALSE edges at input B). | 30 kHz (before firmware V2.0.6) 50 kHz (since firmware V2.0.6) |
| 5 | 1 Up/Down counter with dynamic set/rising edge | A = Counter input B = Dynamic set input |
1 Up/Down counter is available which counts on the rising edge of A and has a dynamic set input on B. Dynamic set input will set the start value at the rising edge of B. | 30 kHz (before firmware V2.0.6) 50 kHz (since firmware V2.0.6) |
| 6 | 1 Up/Down counter with dynamic set/falling edge | A = Counter input B = Dynamic set input |
1 Up/Down counter is available which counts on the rising edge of A and has a dynamic set input on B. Dynamic set input will set the start value at the falling edge of B. | 30 kHz (before firmware V2.0.6) 50 kHz (since firmware V2.0.6) |
| 7 | 1 UpDown directional discriminator | A = Phase A B = Phase B |
With this mode, incremental encoders can be used which give their counting signals on phase A and B in a 90° phase sequence to each other. Dependent on the sequence of the signals at A and B, the counter counts up or down. There is no pulse multiplier function. |
12 kHz (before firmware V2.0.6) 35 kHz (since firmware V2.0.6) |
| 8 | Reserved | - | - | - |
| 9 | 1 UpDown directional discriminator X2 | A = Phase A B = Phase B |
This mode is the same as mode 7 with one exception: There is a pulse multiplication x2 with the evaluation of the counting inputs. This means that the counter counts both the positive edges and the negative edges of phase A. This results in the double number of counting pulses. The precision increases correspondingly. | 11 kHz (before firmware V2.0.6) 30 kHz (since firmware V2.0.6) |
| 10 | 1 UpDown directional discriminator X4 | A = Phase A B = Phase B |
This mode is the same as mode 7 with one exception: There is a pulse multiplication x4 with the evaluation of the counting inputs. This means that the counter counts both the positive edges and the negative edges of phase A and B. This results in the fourfold number of counting pulses. The precision increases correspondingly. | 10 kHz (before firmware V2.0.6) 15 kHz (since firmware V2.0.6) |
Note
If channel 0 is configured as fast counter, the other channels 1,2 and 3 cannot be configured as interrupt inputs. Otherwise, a configuration error will appear and the CPU will be stopped.